1. Field of the Invention
The present invention relates to a substrate bias controlling method adapted to control a substrate bias of a transistor and a semiconductor integrated circuit device in which a substrate bias is controlled by means of the controlling method.
2. Description of the Related Art
In recent years, the number of terminals powered by batteries such as a cell-phone and a mobile information apparatus is on the increase, and built-in semiconductor integrated circuits with lower power consumption have made progress. So far, power consumption has been reduced by lowering supply voltage. Accordingly, although operating speed is decreased, higher operating speed has been accomplished by increasing an ON-current by lowering a threshold voltage of a transistor. However, a leakage current is increased as the semiconductor is further refined and the operating speed grows higher. Accordingly, a leakage current flows inside the semiconductor integrated circuit irrespective of its operation and makes up a significant portion of the power consumption of the semiconductor integrated circuit. Therefore, in order to reduce the power consumption of the semiconductor integrated circuit, it is effective to restrain the leakage current of the transistor. It is known that there is a relationship between the leakage current of the transistor and the ON-current. That is to say, since the ON-current is proportional to a logarithmic value of leakage current, restraint of the leakage current also concurrently restrains the ON-current.
For example, Japanese Laid-Open Patent Application JP2003-142598A discloses a technique adapted simultaneously to carry out compensation for change of an operating speed of a circuit due to manufacturing process and temperature change and compensation for a difference in a threshold voltage between a P-channel transistor and an N-channel transistor by controlling a well bias of the transistor. FIG. 1 is a block diagram showing a configuration of this conventional semiconductor integrated circuit. As shown in FIG. 1, this semiconductor integrated circuit includes a delay monitor circuit 51, a comparison circuit 52, a PN balance compensation circuit 53, and a well bias control circuit 55. The delay monitor circuit 51 delays an input clock and outputs the delayed clock. The comparison circuit 52 compares the input clock with the delayed clock. The PN balance compensation circuit 53 detects threshold voltage difference between a P-channel transistor and a N-channel transistor. The well bias control circuit 55 controls a well bias of the transistor by reflecting the output of the PN balance compensation circuit 53 by means of an adder 56 on the output of the comparison circuit 52.
Next, a bias controlling method of this semiconductor integrated circuit will be described specifically with reference to FIG. 2. FIG. 2 is a graph for explaining the operation of this conventional semiconductor integrated circuit. This drawing mainly shows element characteristics of this semiconductor integrated circuit. The vertical axis shows an ON-current Ionp of the P-channel transistor and the horizontal axis shows an ON-current Ionn of the N-channel transistor. An area enclosed by an alternate long and short dash line 1 indicates an allowable range of the ON-current. An area within the inside of the alternate long and short dash line 1 indicates characteristics of allowable ON-current, that is, allowable leakage current. This area is determined depending on the manufacturing process and the operating requirements such as a supply voltage.
A reference of delay value of the N-channel transistor and the P-channel transistor is indicated by a solid line 2 using an index which is a total value of the ON-current Ionn of the N-channel transistor and the ON-current Ionp of the P-channel transistor. Hereinafter, characteristic indicated by the solid line 2 is referred to as a delay monitor target. A total value of the ON-current Ionn and the ON-current Ionp is preferably close to the delay monitor target 2.
An index showing a balance between the ON-current Ionn and the ON-current Ionp is indicated by a dashed line 3. Hereinafter, the dashed line 3 is referred to as a PN balance monitor target. The ON-current Ionn and the ON-current Ionp are preferably close to the PN balance monitor target 3. Therefore, the ON-current Ionn and the ON-current Ionp are most preferably close to an intersection of the delay monitor target 2 with the PN balance monitor target 3.
A characteristic shown by a point 911 indicates that a sum of the ON-current (Ionn+Ionp) is larger than a sum of the delay monitor target 2 and that the delay value of the N-channel transistor and the P-channel transistor is shorter (operating speed is faster) than the reference value. Moreover, since the point 911 is away from the PN balance monitor target 3, the characteristic shown by the point 911 indicates that the ON-current Ionn and the ON-current Ionp are not balanced. In this case, it is indicated that a threshold voltage of the N-channel transistor is biased to relatively a lower threshold voltage as compared with that of the P-channel transistor.
The characteristic shown by the point 911 turns out to be a characteristic shown by a point 912 when the well bias of the transistor is controlled. In reference to this transition of the characteristics, an adjustment amount varied along the PN balance monitor target 3 as indicated by an arrow 921 corresponds to an amount adjustment of a voltage of the well bias of both the N-channel transistor and the P-channel transistor. Moreover, an adjustment amount varied only in the ON-current Ionn as indicated by an arrow 922 is adjusted because the threshold voltage on the N-channel side is biased to a lower voltage. This corresponds to an adjustment amount due to a voltage rise of the well bias of the N-channel transistor. By means of this adjustment, it is found that the ON-currents of the N-channel transistor and the P-channel transistor come closer to the intersection of the delay monitor target 2 with the PN balance monitor target 3 so that more appropriate well bias will be given.
However, a characteristic shown by a point 951 is similarly adjusted to a characteristic shown by a point 952 by means of adjustment amounts as indicated by arrows 961 and 962. In this case, the characteristic shown by the point 952 is out of the allowable range of the ON-current. This is because the point 952 is out of the allowable range 1 of the ON-current although the point 952 reaches the delay monitor target 2.
As described above, according to the above-mentioned technique, there is a possibility that the ON-currents of the N-channel transistor and the P-channel transistor deviate from the allowable range of the ON-current (leakage current) when a substrate bias is controlled. The manufacturing requirements are set so that the ON-current and the leakage current allowable for the transistor are within a specific range. Application of the substrate bias which yields an ON-current and a leakage current deviating from this allowable range may have an effect on the failure rate of the transistor, and so forth.
Besides, in the above-mentioned document, the balance between the ON-current of the P-channel transistor and the ON-current of the N-channel transistor (corresponding to “balance of leakage currents”, hereinafter referred to as “PN balance”) is monitored by comparing the logical threshold voltage, which is produced by short-circuiting an input and an output of an inverter, with the reference voltage. This method of producing the logical threshold voltage causes increase of power consumption because an electric current passes through the transistors.
In this manner, the substrate bias voltage control circuit is required to control the substrate bias voltage and reduce the leakage current such that the ON-current does not deviate from the allowable range of the ON-current.
It is desired to provide a semiconductor integrated circuit device having a substrate bias voltage control circuit and executing a substrate bias voltage control method, in which an ON-current is hard to deviate from transistor's performance management range and which can supply an appropriate substrate bias voltage.